The present invention relates to a semiconductor memory device. More particularly this invention relates to a layout of a multi-port SRAM (Static Random Access Memory) cell having CMOS construction.
In recent years, there has been an increasing demand for a high-speed processing of electronic devices along with a reduction in weigh and sizes of these devices. The mounting of microcomputers on these electronic devices is now unavoidable. It is also essential to install large-capacity and high-speed processing memories on these microcomputers. Further, along with a rapid distribution of high-performance personal computers, there has also been an increasing demand for large-capacity cache memories. In other words, RAMs that are used by the CPU to execute control programs are required to have a large capacity with high-speed processing.
DRAM (Dynamic RAM) and SRAM are generally used as a RAM. Particularly, SRAM is generally used for cache memories and the like that require high-speed processing. The SRAM is known to have a high-resistance load type memory cell and a CMOS type memory cell. The high-resistance load type is constructed of four transistors and two high-resistance elements. The CMOS type is constructed of six transistors. Because of very small leakage current during data holding, the CMOS type SRAM has high reliability and is used as the main kind of SRAM at present.
Generally a reduction in the area of the memory cell means not only a reduction in the size of the memory cell array but also a realization of high-speed processing. In order to achieve a higher-speed operation of the SRAM than in the past, various layout proposals have been made so far.
For example, according to the semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110, P-well areas and N-well area formed with inverters that constitute a memory cell are disposed so that their boundary lines are parallel with bit lines. Based on this arrangement, diffusion areas within the P-well areas and the N-well area and a cross-connected portion of two inverters are formed in simple shapes respectively having no bending. As a result, the cell area is reduced.
FIG. 21 and FIG. 22 are layout diagrams of the semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110. FIG. 21 shows diffusion areas formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the diffusion areas, and a ground including a first metal-wiring layer. FIG. 22 shows an upper ground including second and third metal-wiring layers formed on the upper layer.
As shown in FIG. 21, in the center of the memory cell, there is disposed the N-well area in which P-channel type MOS transistors P101 and P102 are formed. On both sides of this N-well area, there are formed P-well areas in which N-channel type MOS transistors N101 and N103, and N102 and N104 are formed respectively.
The P-channel type MOS transistors P101 and P102 and the N-channel type MOS transistors N101 and N102 are mutually cross connected to form a CMOS inverter, that is, a flip-flop circuit. The N-channel type MOS transistors N103 and N104 correspond to an access gate (a transfer gate).
As shown in FIG. 22, bit lines BL and /BL are separately formed as second metal-wiring layers. The bit lines BL and /BL are connected to one end of semiconductor terminals of the lower-layer access gate MOS transistors N103 and N104 respectively. A power source line Vdd is formed as a second metal-wiring layer in the center between the bit lines BL and /BL in parallel with these bit lines. The power source line Vdd is connected to one of semiconductor terminals of the lower-layer P-channel type MOS transistors P101 and P102. A word line WL is formed as a third metal-wiring layer in a direction orthogonal with the bit lines BL and /BL. The word line WL is connected to gates of the lower-layer N-channel type MOS transistor N103 and N104. Two ground lines GND are formed as third metal-wiring layers on both sides of the word line WL in parallel with this word line.
As a result of forming the memory cell in this layout, an N-type diffusion area within the P-well area in which the MOS transistors N101 and N103 are located and an N-type diffusion area in which the MOS transistors N102 and N104 are located can be linear and parallel to the bit lines BL and /BL. This construction can prevent occupation of an unnecessary area.
The length of the cell in a lateral direction, that is, the length of the word line WL, is larger than the length of the cell in a longitudinal direction, that is, the length of the bit lines BL and /BL. Therefore, it becomes easy to provide a layout of a sense amplifier connected to the bit lines BL and /BL. At the same time, the number of cells to be connected to one word line can be reduced. As a result, it is possible to reduce a cell current that flows during the reading. In other words, it is possible to reduce power consumption.
The above-described SRAM memory cell is an example of what is called one-port SRAM. In recent years, there has been introduced a multi-processor technique for achieving high-speed processing of computers. Based on this technique, a plurality of CPUs are required to share one memory area. In this aspect, various layouts have been proposed for a multi-port SRAM that makes it possible to have access to CPUs from two ports to the one memory cell.
For example, according to the memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089, a multi-port SRAM construction is realized by disposing a second port in symmetry with a first port on the same layer and by having the two ports formed at the same time. FIG. 23 shows the layout of the memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089.
As shown in FIG. 23, P-channel type MOS transistors P201 and P202 and N-channel type MOS transistors N201xe2x80x2, N202xe2x80x2, N201xe2x80x3 and N202xe2x80x3 are mutually cross connected to form a CMOS inverter, that is, a flip-flop. N-channel type MOS transistors NA, NB, NA2 and NB2 correspond to access gates (transfer gates).
In other words, N-channel type MOS transistors NA and NB make it possible to have an access from one gate via a word line WL1, and N-channel type MOS transistors NA2 and NB2 make it possible to have an access from the other gate via a word line WL2.
Conventional memory cells have a disadvantage that the amount of wiring of the bit lines is large and a delay increases, as the memory cell has a larger length in the direction of the bit lines. The semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110 solves this problem for one-port SRAM.
However, this semiconductor memory device does not solve the above problem for a multi-port SRAM generally having two sets of access gates and a drive-type MOS transistor. The memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089 shows a layout of a multi-port SRAM cell. However, this provides the layout for making it easy to add a second port without generating a large change in the layout of the one-port SRAM cell. This layout does not reduce the size of the multi-port SRAM cell in the direction of the bit lines.
It is an object of the present invention to provide a semiconductor memory device having a memory cell with a short length in the direction of bit lines, in the construction of a P-well area formed with a pair of CMOS inverters and a N-well area that constitute a multi-port SRAM cell. In the semiconductor memory device of the present invention, the P-well area is divided into two P-well areas. The two P-well areas are disposed on the two sides of the N-well area. The boundaries between P and N-well areas are parallel to the bit lines, and a pair of access gates are formed in each of the two P-well areas.
In the semiconductor memory device according to one aspect of the present invention, two P-well areas are provided on the two sides of the N-well area, three (first, third and fifth) N-channel type MOS transistors are electrically connected to the positive-phase bit line and are formed in one P-well area, and three (second, fourth and sixth) N-channel type MOS transistors are connected to the negative-phase bit line and are formed in the other P-well area. The P-well areas and the N-well area are disposed in a direction perpendicular to the positive-phase and negative-phase bitlines. Therefore, it is possible to provide a layout that requires shorter bit lines.
Further, the first and second P-well areas are formed on both sides of the N-well area. According, it is possible to make uniform the distances of wiring connection between the N-channel type MOS transistors formed in the first and second P-well areas respectively and the P-channel type MOS transistors formed in the N-well area.
Further, the first positive-phase bit line, first negative-phase bit line, the second positive-phase bit line, and the second negative-phase bit line extend parallel to boundary lines between the first and second P-well areas and the N-well area respectively. According, it is possible to provide a layout having each bit line formed in a shortest length by taking into consideration a reduction in the length of each word line.
Further, the boundary lines between the first and second P-well areas and the N-well area are perpendicular to the direction in which the first and second word lines extend. Accordingly, it is possible to provide a layout having each word line formed in a shortest length by taking into consideration a reduction in the length of each bit line with priority.
Further, the first P-channel type MOS transistor and the first, third and fourth N-channel type MOS transistors are formed so that respective gate areas are parallel with the extension direction of the first word line and are positioned on the same straight line, and the second P-channel type MOS transistor and the second, fifth and sixth N-channel type MOS transistors are formed so that respective gate areas are parallel with the extension direction of the second word line and are positioned on the same straight line. Accordingly, it is possible to form wires for connecting between the gates in a straight-line shape. Further, as the second P-channel type MOS transistor and the gate areas of the second, fifth and sixth N-channel type MOS transistors are positioned on the same straight line, it is possible to form wires for connecting between the gates in a straight-line shape.
Further, the third and fifth N-channel type MOS transistors are formed in such a manner that respective source diffusion areas and drain diffusion areas are positioned on the same straight line, and are also disposed in parallel with the directions of the extension of the first and second positive-phase bit lines. In addition, the fourth and sixth N-channel type MOS transistors are formed in such a manner that respective source diffusion areas and drain diffusion areas are positioned on the same straight line, and are also disposed in parallel with the directions of the extension of the first and second negative-phase bit lines.
Further, drain diffusion areas of the third and fifth N-channel type MOS transistors are formed in a common first n+ diffusion area, and drain diffusion areas of the fourth and sixth N-channel type MOS transistors are formed in a common second n+ diffusion area. Accordingly, it is possible to reduce the size of the n+ diffusion areas.
Further, drain diffusion area of the first N-channel type MOS transistor and drain diffusion areas of the third and fifth N-channel type MOS transistors are connected to each other by an upper-layer first metal-wiring layer via contact holes, and a drain diffusion area of the second N-channel type MOS transistor and drain diffusion areas of the fourth and sixth N-channel type MOS transistors are connected to each other by an upper-layer second metal-wiring layer via contact holes. Accordingly, it is possible to form the first and second metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas.
Further, the extension direction of the first and second metal-wiring layers is parallel with the extension direction of the first and second word lines. Accordingly, it is possible to optimize the length of the metal-wiring layers like the word lines.
Further, extension directions of the first and second positive-phase bit line, the first and second negative-phase bit lines, the power source line and the GND line respectively are perpendicular to the first and second word lines. Accordingly, it is possible to minimize the respective length of these lines.
Further, drain diffusion areas of the first, third and fifth N-channel type MOS transistors are formed in a common first n+ diffusion area, and drain diffusion areas of the second, fourth and sixth N-channel type MOS transistors are formed in a common second n+ diffusion area. Accordingly, it is possible to omit the metal-wiring layers between these drain diffusion areas.
Further, the first n+ diffusion area and a drain diffusion area of the first P-channel type MOS transistor are connected to each other by an upper-layer first metal-wiring layer via contact holes, and the second n+ diffusion area and a drain diffusion area of the second P-channel type MOS transistor are connected to each other by an upper-layer second metal-wiring layer via contact holes. Accordingly, it is possible to form the metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas and the n+ diffusion areas.
The semiconductor memory device according to another aspect of the present invention comprises a first word line, a second word line, a first positive-phase bit line, a first negative-phase bit line, and a second positive-phase bit line; a first CMOS inverter that structures a CMOS inverter by including a first N-channel type MOS transistor and a first P-channel type MOS transistor; a second CMOS inverter that structures a CMOS inverter by including a second N-channel type MOS transistor and a second P-channel type MOS transistor, and that has an input terminal of the CMOS inverter connected to an output terminal of the first CMOS inverter as a first memory node, and has an output terminal of the CMOS inverter connected to an input terminal of the first CMOS inverter as a second memory node; a third N-channel type MOS transistor that has a gate connected to the first word line, has a drain connected to the first positive-phase bit line, and has a source connected to the first memory node; a fourth N-channel type MOS transistor that has a gate connected to the first word line, has a drain connected to the first negative-phase bit line, and has a source connected to the second memory node; a fifth N-channel type MOS transistor that has a gate connected to the first memory node; and a sixth N-channel type MOS transistor that has a gate connected to the second word line, has a drain connected to the second positive-phase bit line, and has a source connected to a drain of the fifth N-channel type MOS transistor. In addition, first and second P-channel type MOS transistors are formed in an N-well area, the first and third N-channel type MOS transistors are formed in a first P-well area, and the second, fourth, fifth and sixth N-channel type MOS transistors are formed in a second P-well area.
Further, the semiconductor memory device further comprises a third word line, a first positive-phase line, and a second negative-phase bit line; a seventh N-channel type MOS transistor that has a gate connected to the second memory node; and an eighth N-channel type MOS transistor that has a gate connected to the third word line, has a drain connected to the second negative-phase bitline, and has a source connected to a drain of the seventh N-channel type MOS transistor. The seventh and eighth N-channel type MOS transistors are formed in the first P-well area.
Further, the second and third word lines are formed as one common word line.
Further, the first and second P-well areas are formed at both sides of the N-well area.
Further, the respective directions of the extensions of the first positive-phase bit line, the first negative-phase bit line, and the second positive-phase bit line are parallel with a boundary line between the first and second P-well areas and the N-well area.
Further, a boundary line between the first and second P-well areas and the N-well area is orthogonal with directions of respective extensions of the first and second word lines.
Further, the first P-channel type MOS transistor, and the first, fourth and sixth N-channel type MOS transistors are formed such that their respective gate areas are positioned on the same straight line, and are also disposed in parallel with the direction of the extension of the first word line. Further, the second P-channel type MOS transistor, and the second, third and fifth N-channel type MOS transistors are formed such that their respective gate areas are positioned on the same straight line, and are also disposed in parallel with the direction of the extension of the second word line.
Further, the first and third N-channel type MOS transistors are formed such that a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the first positive-phase bit line. Further, the second and fourth N-channel type MOS transistors are formed such that a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the first negative-phase bit line. Further, the fifth and sixth N-channel type MOS transistors are formed such that a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the second positive-phase bit line.
Further, a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are formed in a common first n+ diffusion area. Further, a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are formed in a common second n+ diffusion area. Further, a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are formed in a common third n+ diffusion area.
Further, the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring.
Further, the directions of the extensions of the first and second positive-phase bit lines, the first negative-phase bit line, a power source line, and a GND line respectively are perpendicular to the first and second word lines.
Further, the first P-channel type MOS transistor, and the first, fourth, sixth and seventh N-channel type MOS transistors are formed such that their respective gate areas are in parallel with the direction of the extension of the first word line, and are also positioned on the same straight line. Further, the second P-channel type MOS transistor, and the second, third, fifth and eighth N-channel type MOS transistors are formed such that their respective gate areas are in parallel with the direction of the extension of the second word line, and are also positioned on the same straight line.
Further, the first and third N-channel type MOS transistors are formed such that a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are in parallel with the direction of the extension of the first positive-phase bit line, and are also positioned on the same straight line. Further, the second and fourth N-channel type MOS transistors are formed such that a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are in parallel with the direction of the extension of the first negative-phase bit line, and are also positioned on the same straight line. Further, the fifth and sixth N-channel type MOS transistors are formed such that a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are in parallel with the direction of the extension of the second positive-phase bit line, and are also positioned on the same straight line. Further, the seventh and eighth N-channel type MOS transistors are formed such that a drain diffusion area of the seventh N-channel type MOS transistor and a source diffusion area of the eighth N-channel type MOS transistor are in parallel with the direction of the extension of the second negative-phase bit line, and are also positioned on the same straight line.
Further, a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are formed in a common first n+ diffusion area. Further, a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are formed in a common second n+ diffusion area. Further, a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are formed in a common third n+ diffusion area. Further, a drain diffusion area of the seventh N-channel type MOS transistor and a source diffusion area of the eighth N-channel type MOS transistor are formed in a common fourth n+ diffusion area.
Further, the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common first polysilicon wiring. Further, the first P-channel type MOS transistor, and the first and seventh N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common second polysilicon wiring.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.